(a) Field of the Invention
The present invention relates to a static RAM (SRAM) core cell. More specifically, the present invention relates to a SRAM core cell for a light-emitting display, and is applicable to a data driver of an organic electro-luminescence (EL) light-emitting display device.
(b) Description of the Related Art
The organic EL light-emitting display is a device for displaying an image by controlling a current flowing to an organic material that emits light when the current flows to it. In the organic EL light-emitting display, the organic material is divided by pixels and arranged in a matrix form. The organic EL light-emitting display is promising as a next-generation display device because of its advantages such as low-voltage driving requirement, light weight, slim design, wide viewing angle, rapid response, etc.
FIG. 1 illustrates the principle of light emission of a typical organic EL.
In general, an organic EL light-emitting display, which is a display device that electrically excites a fluorescent organic compound to emit light, drives N×M organic light-emitting cells by voltage or current to represent an image. The organic light-emitting cell has a structure of FIG. 1 that includes an ITO (Indium Tin Oxide) pixel electrode, an organic thin film, and a metal layer. The organic thin film is a multi-layer structure that includes a light-emitting layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL) to keep electrons and holes in good balance and enhance the light-emitting efficiency. The organic thin film may also include an electron injecting layer (EIL) and a hole injecting layer (HIL).
There are typically two driving methods for the organic light-emitting cells: the passive matrix method and the active matrix method using TFTs. The passive matrix method involves selectively driving anode and cathode lines arranged orthogonally to each other, while the active matrix method involves coupling TFTs and capacitors to the respective pixel electrodes and sustaining a voltage according to a capacitor capacity.
FIG. 2 is a schematic block diagram of a typical organic EL display device.
Referring to FIG. 2, the organic EL display device includes a video controller 210, a panel controller 220, a power module 230, a scan driver 240, a data driver 250, and an organic EL panel 260. The scan driver 240 and the data driver 250 supply various signals to the organic EL panel 260 in the column and row directions via analog and digital interfaces, respectively.
More specifically, various analog signals such as R, G, and B signals and sync signals are fed into the video controller 210 and converted into digital signals. The panel controller 220 controls the converted digital signals and supplies them to the scan driver 240 and the data driver 250 in sequence. The organic EL panel 260 drives N×M organic light-emitting cells by voltage or current using the signals supplied from the scan driver 240 and the data driver 250, and the power supplied from the power module 230 to represent an image.
FIG. 3 shows a general active matrix organic EL display panel using TFTs.
Referring to FIG. 3, the organic EL display device includes an organic EL display panel 310, a data driver 320, and a scan driver 330.
The organic EL display panel 310 includes m data lines D1, D2, . . . , Dm arranged in columns; n scan lines S1, S2, . . . , Sn arranged in rows; and n×m pixel circuits. The m data lines D1, D2, . . . , Dm transfer data signals representing image signals to the pixel circuits, and the n scan lines S1, S2, . . . , Sn transfer selection signals to the pixel circuits. Each pixel circuit is formed in one pixel area 310-1 defined by two adjacent ones of the m data lines D1, D2, . . . , Dm, and two adjacent ones of the n scan lines S1, S2, . . . , Sn. The pixel circuit includes, for example, transistors 311 and 312, a capacitor 313, and an organic EL diode 314. Here, reference numeral 315 denotes a power voltage Vdd.
More specifically, each pixel circuit 310-1 includes the organic EL diode (OLED) 314, two transistors 311 and 312, and the capacitor 313. For example, the two transistors 311 and 312 may be PMOS transistors.
The driving transistor 312 has its source coupled to the power voltage Vdd, and the capacitor 313 coupled between its gate and source. The capacitor 313 sustains the gate-source voltage of the driving transistor 312 for a predetermined time period, and the switching transistor 311 transfers a data voltage from the data line Dm to the driving transistor 312 in response to the selection signal from the current scan line Sn.
The organic EL diode 314 has its cathode coupled to a reference voltage Vss, and emits a light corresponding to a current applied through the driving transistor 312. Here, the power Vss coupled to the cathode of the organic EL diode 314 is lower than the power Vdd and can be a ground voltage.
The scan driver 330 sequentially applies the selection signal to the n scan lines S1, S2, . . . , Sn, while the data driver 320 sequentially applies a data voltage corresponding to the image signal to the m data lines D1, D2, . . . , Dm.
The scan driver 330 and/or the data driver 320 may be coupled to the organic EL display panel 310, or mounted as a chip in a tape carrier package (TCP) soldered and coupled to the organic EL display panel 310. Alternatively, the scan driver 330 and/or the data driver 320 may be mounted as a chip in a flexible printed circuit (FPC) or a film soldered and coupled to the display panel 310.
Moreover, the scan driver 330 and/or the data driver 320 may be directly mounted on a glass substrate of the organic EL display panel 310, or substituted by driver circuitry including the same layers of the scan lines, the data lines, and the TFTs on the glass substrate.
FIG. 4 is a circuit diagram of a CMOS SRAM core cell according to prior art.
The CMOS SRAM core cell according to prior art is used with the data driver 320 to implement the organic EL display device as an SOP (System On Package), and is designed as a SRAM having six TFTs. The SRAM stores the data to be displayed on the organic EL panel 260.
Referring to FIG. 4, symbols “MP1” and “MP2” denote pull-up transistors, symbols “MN1” and “MN2” denote pull-down transistors, and symbols “MP3” and “MP4” denote pass transistors for a data access. Here, MP1 to MP4 are PMOS transistors, and MN1 and MN2 are NMOS transistors. The MP1 and the MN1, and the MP2 and the MN2 are implemented as CMOS transistors and arranged in a latch configuration.
In the CMOS RAM core cell according to prior art, a plurality of NMOS and PMOS transistors must be formed with a predetermined width and a predetermined length, with a restriction on a design of the layout, allowing no flexibility of design and causing defects in the fabrication process.